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19-1771; Rev 0; 9/00
Single/Dual LVDS Line Drivers with Ultra-Low Pulse Skew in SOT23
General Description
The MAX9110/MAX9112 single/dual low-voltage differential signaling (LVDS) transmitters are designed for high-speed applications requiring minimum power consumption, space, and noise. Both devices support switching rates exceeding 500Mbps while operating from a single +3.3V supply, and feature ultra-low 250ps (max) pulse skew required for high-resolution imaging applications, such as laser printers and digital copiers. The MAX9110 is a single LVDS transmitter, and the MAX9112 is a dual LVDS transmitter. Both devices conform to the EIA/TIA-644 LVDS standard. They accept LVTTL/CMOS inputs and translate them to low-voltage (350mV) differential outputs, minimizing electromagnetic interference (EMI) and power dissipation. These devices use a current-steering output stage, minimizing power consumption, even at high data rates. The MAX9110/MAX9112 are available in space-saving 8-pin SOT23 and SO packages. Refer to the MAX9111/ MAX9113 data sheet for single/dual LVDS line receivers.
Features
o Low 250ps (max) Pulse Skew for High-Resolution Imaging and High-Speed Interconnect o Space-Saving 8-Pin SOT23 and SO Packages o Pin-Compatible Upgrades to DS90LV017/017A and DS90LV027/027A (SO Packages) o Guaranteed 500Mbps Data Rate o Low 22mW Power Dissipation at 3.3V (31mW for MAX9112) o Conform to EIA/TIA-644 Standard o Single +3.3V Supply o Flow-Through Pinout Simplifies PC Board Layout o Driver Outputs High Impedance when Powered Off
MAX9110/MAX9112
________________________Applications
Laser Printers Digital Copiers Cellular Phone Base Stations Telecom Switching Equipment
Typical Operating Circuit appears at end of data sheet.
Ordering Information
PART MAX9110EKA-T MAX9110ESA MAX9112EKA-T MAX9112ESA TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 8 SOT23-8 8 SO 8 SOT23-8 8 SO TOP MARK AADN -- AADO --
Network Switches/Routers LCD Displays Backplane Interconnect Clock Distribution
Pin Configurations/Functional Diagrams/Truth Table
TOP VIEW
MAX9110
VCC DIN N.C. 1 2 3 8 7 6 5 DODIN 1 2 3
MAX9110
8 7 6 5 DODO+ N.C. N.C. VCC DIN1 DIN2 1 2 3
MAX9112
8 7 6 5 DO1- DIN1 DO1+ GND DO2+ DIN2 DO21 2 3
MAX9112
8 7 6 5 DO1DO1+ DO2+ DO2-
DO+ GND N.C. N.C. N.C.
GND 4
VCC 4
GND 4
VCC 4
SO
SOT23
DIN_ L H 0.8V < VDIN_ < 2.0V DO_+ L H X
SO
DO_H L X H = LOGIC LEVEL HIGH L = LOGIC LEVEL LOW X = UNDETERMINED
SOT23
________________________________________________________________ Maxim Integrated Products
1
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Single/Dual LVDS Line Drivers with Ultra-Low Pulse Skew in SOT23 MAX9110/MAX9112
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC to GND) ..................................-0.3V to +4V Input Voltage (VDIN_ to GND).....................-0.3V to (VCC + 0.3V) Output Voltage (VDO_+, VDO_- to GND or VCC) ...-0.3V to +3.9V Output Short-Circuit Duration (DO_+, DO_- to VCC or GND) ................................Continuous ESD Protection (Human Body Model, DO_+, DO_-)..........11kV Continuous Power Dissipation (TA = +70C) 8-Pin SOT23 (derate 7.52mW/C above +70C)...........602mW 8-Pin SO (derate 5.88mW/C above +70C)...............471mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering,10s) ..................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100 1%, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Notes 1, 2)
PARAMETER Differential Output Voltage Change in Magnitude of Output Voltage for Complementary Output States Offset Voltage Change in Magnitude of Offset Voltage for Complementary Output States Power-Off Leakage Current Short-Circuit Output Current Input High Voltage Input Low Voltage Input Current High Input Current Low No-Load Supply Current Supply Current SYMBOL VOD VOD VOS VOS IO(OFF) Figure 1 Figure 1 Figure 1 Figure 1 VDO_ _ = 0 or VCC, VCC = 0 or open CONDITIONS MIN 250 0 1.125 0 -10 TYP 350 2 1.25 2 MAX 450 35 1.375 25 +10 -20 2.0 GND DIN_ = VCC or 2V DIN_ = GND or 0.8V No load, DIN_ = VCC or 0 DIN_ = VCC or 0 MAX9110 MAX9112 0 -20 10 -3 4.5 6.7 9.4 VCC 0.8 20 0 6 8 13 UNITS mV mV V mV A mA V V A A mA mA
DIN_ = VCC, VDO_+ = 0 or IO(SHORT) DIN_ = GND, VDO_- = 0 VIH VIL IIH IIL ICC ICC
AC CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100 1%, CL = 5pF, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Notes 3, 4, 5; Figures 2, 3)
PARAMETER Differential High-to-Low Propagation Delay Differential Low-to-High Propagation Delay Differential Pulse Skew |tPHLD - tPLHD| (Note 6) Channel-to-Channel Skew (Note 7) SYMBOL tPHLD tPLHD tSKD1 tSKD2 CONDITIONS MIN 1 1 TYP 1.54 1.58 40 70 MAX 2.5 2.5 250 400 UNITS ns ns ps ps
2
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Single/Dual LVDS Line Drivers with Ultra-Low Pulse Skew in SOT23
AC CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, RL = 100 1%, CL = 5pF, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Notes 3, 4, 5; Figures 2, 3)
PARAMETER Part-to-Part Skew High-to-Low Transition Time Low-to-High Transition Time SYMBOL tSKD3 tSKD4 tTHL tTLH (Note 8) (Note 9) 0.25 0.25 0.6 0.6 CONDITIONS MIN TYP MAX 1 1.5 1 1 UNITS ns ns ns
MAX9110/MAX9112
Maximum Operating Frequency fMAX (Note 10) 250 MHz Note 1: Maximum and minimum limits over temperature are guaranteed by design. Devices are production tested at TA = +25C. Note 2: By definition, current into the device is positive and current out of the device is negative. Voltages are referred to device ground except VOD. Note 3: AC parameters are guaranteed by design and characterization. Note 4: CL includes probe and fixture capacitance. Note 5: Signal generator conditions for dynamic tests: VOL = 0, VOH = 3V, f = 20MHz, 50% duty cycle, RO = 50, tR 1ns, and tF 1ns (0 to 100%). Note 6: tSKD1 is the magnitude difference of differential propagation delays in a channel; tSKD1 = | tPHLD - tPLHD |. Note 7: tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of the other channel on the same device (MAX9112). Note 8: tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and within 5C of each other. Note 9: tSKD4 is the magnitude difference of any differential propagation delays between devices operating over the rated supply and temperature ranges. Note 10: fMAX signal generator conditions: VOL = 0, VOH = +3V, frequency = 250MHz, tR 1ns, tF 1ns (0 to 100%) 50% duty cycle. Transmitter output criteria: duty cycle = 45% to 55%, VOD 250mV.
Typical Operating Characteristics
(VCC = +3.3V, RL = 100, CL = 5pF, VIH = +3V, VIL = GND, fIN = 20MHz, TA = +25C, unless otherwise noted.) (Figures 2, 3)
MAX9110 SUPPLY CURRENT vs. INPUT FREQUENCY
A: VCC = +3.0V B: VCC = +3.3V C: VCC = +3.6V
MAX9110 toc01
SUPPLY CURRENT vs. TEMPERATURE
7.3 7.2 CURRENT SUPPLY (mA) 7.1 7.0 6.9 6.8 6.7 6.6 6.5
MAX9110 toc02
DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE
MAX9110 toc03
9.5 9.0 SUPPLY CURRENT (mA) 8.5 8.0 7.5 A 7.0 6.5 1 100 10k 1M 100M B C
7.4
2.0 1.8 PROPAGATION DELAY (ns) 1.6 1.4 1.2 1.0 0.8 tPHLD tPLHD
6.4 1G -40 -15 10 35 60 85 INPUT FREQUENCY (Hz) TEMPERATURE (C)
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
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Single/Dual LVDS Line Drivers with Ultra-Low Pulse Skew in SOT23 MAX9110/MAX9112
Typical Operating Characteristics (continued)
(VCC = +3.3V, RL = 100, CL = 5pF, VIH = +3V, VIL = GND, fIN = 20MHz, TA = +25C, unless otherwise noted.) (Figures 2, 3)
DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
MAX9110 toc04
DIFFERENTIAL PULSE SKEW vs. SUPPLY VOLTAGE
MAX9110 toc05
DIFFERENTIAL PULSE SKEW vs. TEMPERATURE
MAX9110 toc06
2.0 1.8 PROPAGATION DELAY (ns) 1.6 1.4 1.2 1.0 0.8 -40 -15 10 35 60 tPLHD tPHLD
100 DIFFERENTIAL PULSE SKEW (ps)
100 DIFFERENTIAL PULSE SKEW (ps)
80
80
60
60
40
40
20
20
0 85 3.0 3.1 3.2 3.3 3.4 3.5 3.6 TEMPERATURE (C) SUPPLY VOLTAGE (V)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
TRANSITION TIME vs. SUPPLY VOLTAGE
MAX9110 toc07
TRANSITION TIME vs. TEMPERATURE
MAX9110 toc08
OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
1.45 1.40 OUTPUT VOLTAGE (V) 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 OUTPUT LOW OUTPUT HIGH
MAX9110 toc09
700 650 TRANSITION TIME (ps) 600 550 500 450 400 350 300 3.0 3.1 3.2 3.3 3.4 3.5 tTLH tTHL
600 580 560 TRANSITION TIME (ps) 540 520 500 480 460 440 420 400 tTHL tTLH
1.50
3.6
-40
-15
10
35
60
85
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
DIFFERENTIAL OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
MAX9110 toc10
DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTANCE
DIFFERENTIAL OUTPUT VOLTAGE (mV) 425 400 375 350 325 300 275 250 75.0 87.5 100.0 112.5 125.0 137.5 150.0 VCC = +3.6V VCC = +3V
MAX9110 toc11
450 DIFFERENTIAL OUTPUT VOLTAGE (mV) 425 400 375 350 325 300 275 250 3.0 3.1 3.2 3.3 3.4 3.5
450 VCC = +3.3V
3.6
SUPPLY VOLTAGE (V)
LOAD RESISTANCE ()
4
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Single/Dual LVDS Line Drivers with Ultra-Low Pulse Skew in SOT23
Typical Operating Characteristics (continued)
(VCC = +3.3V, RL = 100, CL = 5pF, VIH = +3V, VIL = GND, fIN = 20MHz, TA = +25C, unless otherwise noted.) (Figures 2, 3)
OUTPUT HIGH VOLTAGE vs. LOAD RESISTANCE
MAX9110 toc12
MAX9110/MAX9112
OUTPUT LOW VOLTAGE vs. LOAD RESISTANCE
1.09 OUTPUT LOW VOLTAGE (V) 1.08 1.07 1.06 1.05 1.04 1.03 1.02 1.01 1.00 VCC = +3V VCC = +3.3V VCC = +3.6V
MAX9110 toc13
1.45 1.44 OUTPUT HIGH VOLTAGE (V) 1.43 1.42 1.41 1.40 1.39 1.38 1.37 1.36 1.35 75.0 87.5 100.0 112.5 125.0 137.5 VCC = +3.3V VCC = +3V VCC = +3.6V
1.10
150.0
75.0
87.5
100.0
112.5
125.0
137.5
150.0
LOAD RESISTANCE ()
LOAD RESISTANCE ()
Pin Description
PIN MAX9110 SOT23 4 1 -- 3, 5, 6 2 7 -- 8 -- SO 1 2 -- 3, 5, 6 4 7 -- 8 -- SOT23 4 -- 1, 3 -- 2 -- 6, 7 -- 5, 8 MAX9112 SO 1 -- 2, 3 -- 4 -- 6, 7 -- 5, 8 VCC DIN Transmitter Input DIN1, DIN2 N.C. GND DO+ Noninverting Transmitter Output DO2+, DO1+ DOInverting Transmitter Output DO2-, DO1No Connection. Not internally connected. Ground Positive Supply NAME FUNCTION
Detailed Description
The MAX9110/MAX9112 single/dual LVDS transmitters are intended for high-speed, point-to-point, low-power applications. These devices accept CMOS/LVTTL inputs with data rates exceeding 500Mbps. The MAX9110/MAX9112 reduce power consumption and
EMI by translating these signals to a differential voltage in the 250mV to 450mV range across a 100 load while drawing only 9.4mA of supply current for the dualchannel MAX9112. A current-steering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The output
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Single/Dual LVDS Line Drivers with Ultra-Low Pulse Skew in SOT23 MAX9110/MAX9112
DO_+ CL DO_ + VOS RL/2 VOD
S
RL/2 VCC GND DIN_ GENERATOR DIN_ RL
VO
50 CL
DO_ -
DO_-
Figure 1. LVDS Transmitter VOD and VOS Test Circuit
Figure 2. Transmitter Propagation Delay and Transition Time Test Circuit
3V DIN_ 1.5V 1.5V 0 tPLHD DO_ 0V DIFFERENTIAL DO_+ 0 VOL 80% 0 VDIFF 20% tTLH tTHL VDIFF = VDO_+ - VDO_80% 0 20% tPHLD VOH
Figure 3. Transmitter Propagation Delay and Transition Time Waveforms
stage presents a symmetrical, high-impedance output, reducing differential reflection and timing distortion. The driver outputs are short circuit current limited and enter a high-impedance state when the device is not powered.
LVDS Operation
The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled impedance medium as defined by the EIA/TIA644 LVDS standard. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. LVDS transmitters such as the MAX9110/MAX9112 convert CMOS/LVTTL signals to low-voltage differential signals at rates in excess of 500Mbps. The MAX9110/ MAX9112 current-steering architecture requires a resistive load to terminate the signal and complete the trans6
mission loop. Because the device switches the direction of current flow and not voltage levels, the actual output voltage swing is determined by the value of the termination resistor at the input of an LVDS receiver. Logic states are determined by the direction of current flow through the termination resistor. With a typical 3.5mA output current, the MAX9110/MAX9112 produce an output voltage of 350mV when driving a 100 load. The steady-state-voltage peak-to-peak swing is twice the differential voltage, or 700mV (typ).
Applications Information
Supply Bypassing
Bypass VCC with high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel, as close to the device as possible, with the smaller valued capacitor the closest. For additional supply bypassing, place a 10F tantalum or ceramic capacitor at the point where power enters the circuit board.
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Single/Dual LVDS Line Drivers with Ultra-Low Pulse Skew in SOT23
Differential Traces
Output trace characteristics affect the performance of the MAX9110/MAX9112. Use controlled impedance traces to match trace impedance to both transmission medium impedance and termination resistor. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Maintain the distance between the differential traces to avoid discontinuities in impedance. Avoid 90 turns and minimize the number of vias to further prevent impedance discontinuities.
+3.3V
Board Layout
For LVDS applications, a four-layer PC board that provides separate power, ground, LVDS signals, and input signals is recommended. Isolate the input and LVDS signals from each other to prevent coupling. Separate the input and LVDS signal planes with the power and ground planes for best results.
MAX9110/MAX9112
Typical Operating Circuit
+3.3V 0.001F 0.1F 0.001F 0.1F
Cables and Connectors
Transmission media should have a differential characteristic impedance of about 100. Use cables and connectors that have matched impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables, such as ribbon or simple coaxial cable. Balanced cables, such as twisted pair, offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver.
DIN_
DRIVER
RT = 100
RECEIVER
OUT_
LVDS
MAX9110 MAX9112
MAX9111 MAX9113
Termination
Termination resistors should match the differential characteristic impedance of the transmission line. Because the MAX9110/MAX9112 are current-steering devices, an output voltage will not be generated without a termination resistor. Output voltage levels are dependent upon the termination resistor value. Resistance values may range between 75 and 150. Minimize the distance between the termination resistor and receiver inputs. Use a single 1% to 2% surfacemount resistor across the receiver inputs.
Chip Information
MAX9110 TRANSISTOR COUNT: 765 MAX9112 TRANSISTOR COUNT: 765 PROCESS: CMOS
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Single/Dual LVDS Line Drivers with Ultra-Low Pulse Skew in SOT23 MAX9110/MAX9112
Package Information
SOT23, 8L.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
SOICN.EPS

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